VLSI Projects 2011 available @ NCCT, (VLSI FPGA Projects Spartan FPGA Kit, Xilinx) for more details www.ncct.in, Contact - 044-28235816, 98411 93224, 93801 02891, ncctchennai@gmail.com ...... For Project Titles, Abstracts Downloads visit www.ncct.in

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Thursday, September 22, 2011


VLSI PROJECT LIST, IEEE 2011 

  • A formal approach to designing cryptographic processor.
  • A novel low power and high speed Wallace tree multiplier for RISC processor.
  • A review on power optimization of linear feedback shift register for low power built in self test
  • An ultra low power BPSK receiver and demodulator based on injection locked oscillator.
  • Coping With the Obsolescence of Safety- or Mission-Critical Embedded Systems Using FPGAs
  • Efficient iterative techniques for soft decision decoding of reed Solomon codes.
  • FPGA Based Electronics for PET Detector Modules With Neural Network Position Estimators.
  • FPGA Design for Monitoring CAN bus Traffic in a Prosthetic Limb Sensor Network.
  • FPGA Implementation of BPSK Modem for Telemetry Systems Operating in Noisy Environments
  • FPGA-Based Configurable Frequency-Diverse Ultrasonic Target-Detection System.
  • FPGA-Based Parallel DNA Algorithm for Optimal Configurations of an Omni directional Mobile Service Robot
  • Performing Fire Extinguishment FPGAs in Industrial Control Applications.
  • Hardware-Efficient Image-Based Robotic Path Planning in a Dynamic Environment and Its FPGA Implementation.
  • Mapping multi-domain applications onto coarse-grained reconfigurable architectures.
 www.ncct.in, ncctchennai@gmail.com, 2823 5816, 984 11 93 224

  • Removal of impulse noise using 3x3 kernel FPGA implementation
  • Systematic design of RSA processors based on high-radix Montgomery multipliers.
  • The SoC Design and Realization of Small Scale Solar Irrigation Control System Based on FPGA.
  • Ultra wideband digital receiver implemented on FPGA for mobile robot indoor self-localization.
  • A Median Filter Fpga With Harvard Architecture
  • A New Adaptive Weight Algorithm For Salt And Pepper Noise Removal
  • A Pipeline Vlsi Architecture For High-Speed Computation Of The 1-D  Discrete Wavelet Transform
  • Adiabatic Technique For Energy Efficient Logic Circuits Design
  • An Fpga-Based Architecture For Linear And Morphological Image Filtering
  • Automatic Road Extraction Using High Resolution Satellite Images Based On Level Set And Mean Shift Methods
  • Design And Fpga Implementation Of Modified Distributive Arithmetic Based Dwt-Idwt Processor For Image Compression
  • Design Of A Low Power Flip-Flop Using Cmos Deep Submicron Technology
  • Detecting Background Setting For Dynamic Scene
  • Dual Stack Method A Novel Approach To Low Leakage And Speed Power Product Vlsi Design
  • Lossless Implementation Of Daubechies 8-Tap Wavelet Transform
  • Low-Power And Area-Efficient Carry Select Adder
  • Operation Improvement Of Indoor Robot By Gesture Recognition
  • Performance Analysis Of Integer Wavelet Transform For Image Compression
  • Removal Of High Density Salt And Pepper Noise Through Modified Decision Based Unsymmetric Trimmed Median Filter
 www.ncct.in, ncctchennai@gmail.com, 2823 5816, 984 11 93 224

  • 4 Bit SFQ Multiplier based on Booth Encoder
  • A Lightweight High-Performance Fault Detection Scheme For The Advanced Encryption Standard Using Composite Fields
  • A Rotation-Based BIST With Self-Feedback Logic To Achieve Complete Fault Coverage
  • An Autonomous Vectorscalar Floating Point Coprocessor For FPGAS
  • Building An AMBA AHB Compliant Memory Controller
  • Design And Characterization Of Parallel Prefix Adders Using FPGAS
  • Design And Implementation Of Cordic Processor For Complex DPLL
  • Direct Digital Frequency Synthesizer Using Nonuniform Piecewise-Linear Approximation
  • FPGA Based Real-Time Adaptive Fuzzy Logic Controller
  • High Speed ASIC Design Of Complex Multiplier Using Vedic Mathematics
www.ncct.in, ncctchennai@gmail.com, 2823 5816, 984 11 93 224

  • High-Accuracy Fixed-Width Modified Booth Multipliers For Lossy Applications
  • High-Speed Low-Power VITERBI Decoder Design For TCM Decoders
  • Ieee 1451-Based Multi-Interface Module (I2M) For Industrial Processes Automation
  • Implementation And Performance Analysis Of Seal Encryption On FPGA, GPU And Multi-Core Processors
  • Innovative Application Of RFID Systems To Special Education Schools
  • Low-Complexity Sequential Searcher For Robust Symbol Synchronization In OFDM Systems
  • Mobile Video Monitoring System Based On FPGA & GPRS
  • On The Transmission Method For Short Range MIMO Communications
  • Power Management Of MIMO Network Interfaces On Mobile Systems
  • PVT Variation Tolerant Current Source With On-Chip Digital Self-Calibration
  • Task Migration In Mesh NOCS Over Virtual Point-To-Point Connections
  • Technique Of LFSR Based Test Generator Synthesis For Deterministic And Pseudorandom Testing
 www.ncct.in, ncctchennai@gmail.com, 2823 5816, 984 11 93 224
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